library IEEE;
use  IEEE.STD_LOGIC_1164.all;

entity Clock_Divider is
	port(
	inCLK	: in std_logic;
	outCLK	: out std_logic
	);
end entity;

architecture arch_1 of Clock_Divider is
	signal count			: integer range 0 to 1;
begin	
	process
	begin
	wait until (inCLK'event AND inCLK = '1');
	
	if(count = 1) then
		count <= 0;
		outCLK <= '0';
	else
		count <= count + 1;
		outCLK <= '1';
	end if;	
	end process;
		
end architecture;